Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs
نویسندگان
چکیده
An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which allow to represent gate level circuits at higher macro level where macros represent subnetworks of gates. Converting the gate-level circuits to the macrolevel is accompanied with corresponding fault collapsing. A parallel fault analysis algorithm for SSBDDs was developed which calculates the detected representative faults for a given set of test patterns in the corresponding macro. The algorithm is equivalent to parallel critical path tracing in the gate-level circuits of macros. Because of the reduced fault list and higher abstraction level modeling the speed of fault simulation is increased. For the faults in fanout nodes a new full Boolean differentials based parallel fault analysis method is proposed. The paper presents experimental data revealing the advantages of the proposed data structure in the fault simulation process
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